1. Field of the Invention
The invention relates to a method and to an encoder for encoding a data word for writing the encoded data word in N cells of a solid state memory. Further, the invention relates to a method and to a decoder for decoding a codeword written in N cells of a solid state memory.
2. Description of Related Art
A solid state memory uses electronic circuitry, such as integrated circuits, for storing data or data words rather than conventional magnetic or optical media like disks and tapes. Solid state storage devices such as flash memory devices are currently revolutionizing the data storage landscape. These devices are more rugged than conventional storage devices due to the absence of moving parts, and offer exceptional bandwidth, significant savings in power consumption, and random I/O (input/output) performance that is orders of magnitude better than hard disk drives (HDDs).
In some types of solid state memory, the fundamental storage unit, called the cell, can be set to only two levels for recording only binary values. Other types of solid state memory have so-called multi-level cells which can be set to q different levels, where q>2. For example, flash memory and phase change memory (PCM), two important non-volatile memory technologies, permit such multi-level recording. For instance, NOR flash memories can store four levels, i.e. two bits, per cell. Multi-level cell (MLC) NAND flash memory chips that can store four bits of data per single flash cell using 43 nm process technology are available.
PCM is a non-volatile solid state memory technology that exploits a reversible, thermally-assisted switching of certain chalcogenide and non-chalcogenide compounds between certain states of different electrical conductivity.
PCM is a promising and advanced emerging non-volatile memory technology mainly due to its excellent features including low latency, high endurance, long retention and high scalability. PCM can be considered a prime candidate for flash replacement, embedded/hybrid memory and storage-class memory. Key requirements for competitiveness of PCM technology are multi-level cell functionality, in particular for low cost per bit; further requirements are high-speed read/write operations, in particular for high bandwidth. Multilevel functionality, i.e., multiple bits per PCM cell, is a way to increase capacity and thereby to reduce cost.
Multi-level PCM is based on storing multiple resistance levels between a lowest (SET) and a highest (RESET) resistance value. Multiple resistance levels or simply levels correspond to partial-amorphous and partial-crystalline phase distributions of the phase-change material of the PCM cell. Phase transformation, i.e., memory programming, can be enabled by Joule heating. In this regard, Joule heating can be controlled by a programming current or voltage pulse. Storing multiple resistance levels in a PCM cell is a challenging task. Issues like process variability, as well as intra-cell and inter-cell material parameter variations can give rise to deviations of the achieved resistance levels from their intended values.
For instance, in single-step programming approaches, single write pulses are applied in order to amorphize or crystallize a certain fraction of the phase change material of the PCM cell. The amplitude of the programming pulse is determined by the characteristic R-I programming curve of the PCM cell. Although, the programming curves of various cells exhibit similar overall behavior, there are variations of the PCM cells that can cause variations of the programmed levels in multi-level storage.
In particular, the cells in a large PCM array can show some variability of the electrical behavior. The same write signal can not result in exactly the same state of each cell generally. As a result, when probing the cell to read-out its state, there can be a cell-to-cell variability of the read-back signal, that is the inferred resistance level or any other metric, which is indicative of the cell's state, can vary from cell to cell.
Conventionally, this variability can be compensated by an adaptive iterative write scheme. A cell can be considered to be correctly written if the read-back signal lies within a predefined range around the written nominal level. However, a few cells can be partially-defective and allow only a limited range of resistance values to be written correctly. Because these partially-defective cells can not support writing all the nominal levels within the full resistance range of the PCM array, multilevel coding can be not possible. The range limitation in partially-defective cells can, for example, affect the high resistance values close to the reset state, or it can affect the low resistance values close to the set state, depending on the cell characteristics. A coding method proposed in L. A. Lastras, et al., “Algorithms for memories with stuck cells,” Proc. IEEE SIT 2010, Austin, June 2010, pp. 968-972 is based on linear BCH-like codes.